1. Field of the Invention
The present invention relates to a process for producing a semiconductor device having field effect transistors (FETs).
2. Description of the Prior Art
The conventional process for producing an FET will first be explained with reference to FIG. 1, wherein a standard structure for a metal-insulator-semiconductor FET (MISFET) device or a metal-oxide-semiconductor FET (MOSFET) device is illustrated. In FIG. 1, the MOSFET comprises a silicon body or substrate 1. The silicon substrate 1 has a P type conductivity when the MOSFET is an N channel transistor. A field oxide film 2 is formed on the silicon substrate 1 and surrounds the substrate surface where the source, drain and gate regions are to be formed. A gate oxide film 3 is formed on the silicon substrate 1 and a polycrystalline silicon gate 4 is formed on the gate oxide film 3. N.sup.+ type source and drain regions 5 and 6, respectively, are exposed within windows 8 and 9 of a phosphosilicate glass (PSG) film 7. Contact electrodes 10 and 11 are brought into ohmic contact with the source region 5 and drain region 6, respectively, via the windows 8 and 9.
In the formation of the MOSFET, the source region 5 and the drain region 6 are usually produced by the ion implantation of impurities using the polycrystalline silicon gate 4 as a mask. After the formation of the source and drain regions, the windows 8 and 9 are formed through the PSG film 7 so as to expose surface portions of these regions. This means that, since a mask used in the photolithographic process of the window formation may be misaligned with the theoretical position of the windows, the dimensions of the source and drain regions 5 and 6, respectively, must be large enough to ensure exposure of such surface portions. The width (W.sub.2) of the PSG film 7 covering the polycrystalline silicon gate 4 and the source or drain region, and the width (W.sub.4) of the PSG film 7 covering the field oxide film are approximately from 2 to 3 microns. The width (W.sub.3) of the exposed source or drain portion is approximately 3 microns and the width (W.sub.1) of the gate oxide film 3 is approximately 3 microns.
The MOSFETs produced by the conventional process as illustrated above have disadvantageously large dimensions due to the widths (W.sub.2, W.sub.3 and W.sub.4). It is to be noted in this regard that, although the width (W.sub.1) of the gate oxide film 3 is important for determining the electrical characteristics of the MOSFETs, the widths (W.sub.2, W.sub.3 and W.sub.4) do not influence the electrical characteristics, but merely influence the alignment procedure of the photolithographic mask for the formation of the windows 8 and 9.
In FIG. 2, a semiconductor memory device including an MOSFET is illustrated. In FIG. 2 the same members as those in FIG. 1 have the same reference numerals. Reference numerals 12, 24 and 25 indicate an oxide film of a capacitor, a capacitor gate and a protecting oxide film of a capacitance element of the semiconductor memory device, respectively. Since both oxide films 3 and 25 are formed simultaneously by oxidation of silicon, the thickness of the relatively thick oxide film 25 is not so great as to prevent a short circuit between the polycrystalline silicon gate 4 and the capacitor gate 24 via the oxide film 25.
Referring again to FIG. 1, in order to enhance the electrical characteristics of the MOSFET, the dimensions of the elements of the MOSFET, particularly the channel length, i.e. the width (W.sub.1), should be reduced. When such dimensions are small, the parasitic capacitance of the various elements of the MOSFET is low and the gain and speed of the MOSFET are high. When the channel length is decreased below a certain value l.sub.0 indicated in FIG. 3, the threshold voltage (V.sub.TH) of the surface of the silicon substrate 1 (FIG. 1), when the channel is formed, is decreased as shown by the curve in FIG. 3. When the channel length is less than the l.sub.0 mentioned above, the threshold voltage is greatly dependent on the forming accuracy of the N.sup.+ type source and drain regions 5 and 6, respectively, which disadvantageously leads to the generation of a large variance in the electrical characteristics of the MOSFETs within a wafer or production lots.
The channel length has, therefore, been adjusted to a value more than the l.sub.0 mentioned above, where the threshold voltage is relatively constant. The phenomenon illustrated in FIG. 3 has been studied by researchers and the reason such phenomenon is caused has been proven to be that a lateral electric field in the channel region is greatly influenced by the voltage applied to the N.sup.+ type drain region.